1. Field of the Invention
The present invention is directed generally to a multichannel communication processing system, and more particularly, to frame processing means for processing a plurality of frames by use of a set of a CPU, a DMA control module and so on.
2. Description of Background
A conventional system for processing a communication protocol is disclosed in, e.g., Japanese Patent Laid-Open No. 144839/1989. FIG. 2 illustrates a construction of this conventional system.
A communication processing system 2 comprises a line control module 21, a transmitting/receiving FIFO (first-in first-out) memory 22, a DMA control module 23, a memory 24, a CPU 25 and an internal bus 26. The line control module 21 effects a serial interface with a remote station through transmitting/receiving lines. The memory 22 temporarily stores the transmitting/receiving data. The DMA control module 23 transfers the data directly to a main memory 3 on the side of a host processor 4. The memory 24 stores a communication processing program and the data. The CPU 25 controls the communication processing system 2 as a whole. The bus 26 connects circuits thereof.
The communication processing system 2 is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit processing technology to provide LSI.
The communication processing system LSI 2 is employed for processing a link access procedure-on D channel LAPD serving as a communication protocol of, e.g., an integrated services digital network ISDN. In this case, a transmitting/receiving line rate is 16 or 64 kbps, while an operating system clock of the internal CPU 25 is, for instance, 6 MHz.
The conventional technology described above is limited to a case where only one transmitting/receiving line is prepared. No consideration is given to an application to a system having a plurality of lines. Hence, when constructing the system which, as in a station exchange or a private branch exchange, accommodates a plurality, particularly, a multiplicity of lines, it is required that the communication processing systems LSI2 be used one by one for every line. This results in a scale-up of the whole system and an increase in costs as well.
The transmitting/receiving line rate of 16 kbps or 64 kbps amounts to approximately 1/380 and 1/100, of the system clock of 6 MHz. Thus the transmitting/receiving line rate of 16 kbps or 64 kbps is very low speed as compared with the operating system clock of 6 MHz of the built-in CPU 25. Hence, the time for waiting for an interruption from the line control module 21 or the DMA control module 23 is much longer than in a state where the built-in CPU 25 works to control the single transmitting/receiving line. The communication processing system LSI2 is therefore inefficient.